Fen Ge

According to our database, Fen Ge authored at least 52 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Lightweight BiSeNet Embedded with YOLOv5 Feature Fusion Network.

Jin Zhao, Fang Zhou, Fen Ge, Shuning Wu, Hao Wang

Proceedings of the 23rd IEEE International Conference on Communication Technology, 2023

A Deep Q Network Hardware Accelerator Based on Heterogeneous Computing.

Guohui Zhang, Fen Ge, Fang Zhou

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Method of Mapping Convolutional Neural Networks on Resource-limited NoC Platform.

Jiantao Ye, Fen Ge, Fang Zhou

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture.

Wenqiang Gong, Fang Zhou, Fen Ge

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

The Design of a Novel Hardware Trojan without Inactive Signal for AES.

Kaiyu Zhao, Fang Zhou, Ning Wu, Jin Zhao, Fen Ge

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

A Hybrid CNN Compression Approach for Hardware Acceleration.

Xin Yue, Fen Ge, Fang Zhou, Ning Wu, Yi Zhang

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

A Defense Method Against Persistent Fault Attack.

Zhixiang Xu, Ning Wu, Fang Zhou, Fen Ge

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

A Vehicle Line-Pressing Detection Approach Based on YOLOv5 and DeepSort.

Shuning Wu, Fen Ge, Yi Zhang

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m).

Xinyu Wang, Ning Wu, Fang Zhou, Fen Ge

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Implementation of Bidirectional LSTM Accelerator Based on FPGA.

Hao Wang, Danfeng Qiu, Fen Ge, Ying Yang

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units.

Ziyu Li, Fen Ge, Fang Zhou, Ning Wu

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection.

Wang Han, Ning Wu, Fang Zhou, Fen Ge

Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

2021

Highly efficient architecture of elliptic curve scalar multiplication with fault tolerance over GF(2^m).

Fang Zhou, Caixian Fei, Ning Wu, Fen Ge

IEICE Electron. Express, 2021

Collaborative thermal- and traffic-aware adaptive routing scheme for 3D network-on-chip systems.

Lili Shen, Ning Wu, Gaizhen Yan, Fen Ge

IEICE Electron. Express, 2021

Implementation of Reconfigurable CNN-LSTM Accelerator Based on FPGA.

Ying Yang, Fen Ge, Danfeng Qiu, Xin Yue, Ziyu Li, Fang Zhou, Ning Wu

Proceedings of the 21st International Conference on Communication Technology, 2021

An Anti-DPA Elliptic Curve Cryptography Scalar Multiplier with Randomized Base Point.

Jin Wen, Ning Wu, Fen Ge, Fang Zhou, Zhixiang Xu, Benjun Zhang

Proceedings of the 21st International Conference on Communication Technology, 2021

Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning.

Tong Lu, Fang Zhou, Ning Wu, Fen Ge, Benjun Zhang

Proceedings of the 21st International Conference on Communication Technology, 2021

Design and Implementation of OpenCL-Based FPGA Accelerator for YOLOv2.

Chenchen Cui, Fen Ge, Ziyu Li, Xin Yue, Fang Zhou, Ning Wu

Proceedings of the 21st International Conference on Communication Technology, 2021

2020

Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation.

Hao Xiao, Yanming Fan, Fen Ge, Zhang Zhang, Xin Cheng

IEICE Trans. Inf. Syst., 2020

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping.

Wentao Xu, Ning Wu, Fen Ge

IEICE Electron. Express, 2020

A Dynamic Branch Predictor Based on Parallel Structure of SRNN.

Lei Zhang, Ning Wu, Fen Ge, Fang Zhou, Mahammad Rehan Yahya

IEEE Access, 2020

Small Area Configurable Deep Neural Network Accelerator for IoT System.

Liangkai Zhao, Ning Wu, Fen Ge, Fang Zhou, Jiahui Zhang, Tong Lu

Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

A Mapping Method for Convolutional Neural Networks on Network-on-Chip.

Yayue Zhao, Fen Ge, Chenchen Cui, Fang Zhou, Ning Wu

Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

Design and Implementation of LSTM Accelerator Based on FPGA.

Weifeng Zhang, Fen Ge, Chenchen Cui, Ying Yang, Fang Zhou, Ning Wu

Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

Differential Fault Attack for the Iterative Operation of AES-192 Key Expansion.

Liang Han, Ning Wu, Fen Ge, Fang Zhou, Jin Wen, Peiyao Qing

Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

A Scalable Bit-Parallel Word-Serial Multiplier with Fault Detection on GF(2^m).

Caixian Fei, Fang Zhou, Ning Wu, Fen Ge, Jin Wen, Peiyao Qin

Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

2019

Machine learning-based dynamic reconfiguration algorithm for reconfigurable NoCs.

Yafei Zhang, Ning Wu, Gaizhen Yan, Fen Ge

IEICE Electron. Express, 2019

RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs.

Muhammad Rehan Yahya, Ning Wu, Gaizhen Yan, Fen Ge, Tanveer Ahmed

IEICE Electron. Express, 2019

Fault attack hardware Trojan detection method based on ring oscillator.

Qiangjia Bi, Ning Wu, Fang Zhou, Jinbao Zhang, Muhammad Rehan Yahya, Fen Ge

IEICE Electron. Express, 2019

Srax: A Low Crosstalk and Insertion Loss 5×5 Optical Router for Optical Network-on-Chip.

Xinhao Shi, Ning Wu, Fen Ge, Gaizhen Yan, Yan Xing, Xudong Ma

Proceedings of the IECON 2019, 2019

A dual-threshold credit-based flow control mechanism for 3D Network-on-Chip.

Xiangli Li, Fen Ge, Ben Rui, Ning Wu, Fang Zhou

Proceedings of the International Conference on IC Design and Technology, 2019

2018

Countermeasure against fault sensitivity analysis based on clock check block.

Jinbao Zhang, Ning Wu, Fen Ge, Fang Zhou, Xiaoqing Zhang

IEICE Electron. Express, 2018

2017

Collaborative fuzzy-based partially-throttling dynamic thermal management scheme for three-dimensional networks-on-chip.

Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou

IET Comput. Digit. Tech., 2017

ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation.

Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou

IEICE Electron. Express, 2017

Thermal-aware task mapping for communication energy minimization on 3D NoC.

Lili Shen, Ning Wu, Gaizhen Yan, Fen Ge

IEICE Electron. Express, 2017

2016

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.

Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie

IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Synchronization for Distributed Embedded Multiprocessors.

Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang

IEEE Trans. Very Large Scale Integr. Syst., 2016

Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box.

Xiaoqiang Zhang, Ning Wu, Fang Zhou, Fen Ge

J. Circuits Syst. Comput., 2016

A MapReduce architecture for embedded multiprocessor system-on-chips.

Hao Xiao, Huajuan Zhang, Fen Ge, Ning Wu

IEICE Electron. Express, 2016

MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints.

Gui Feng, Fen Ge, Ning Wu, Lei Zhou, Jing Liu

IEICE Electron. Express, 2016

2015

Distributed Synchronization for Message-Passing Based Embedded Multiprocessors.

Hao Xiao, Ning Wu, Fen Ge, Guanyu Zhu, Lei Zhou

IEICE Trans. Inf. Syst., 2015

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA.

Jintao Zheng, Ning Wu, Gaizhen Yan, Fen Ge, Lei Zhou

IEICE Electron. Express, 2015

The Adaptive Thermal and Traffic-Balanced Routing algorithm based on temperature analysis and traffic statistics.

Zhiping Wu, Ning Wu, Lei Zhou, Fen Ge

IEICE Electron. Express, 2015

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.

Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

DimNoC: a dim silicon approach towards power-efficient on-chip network.

Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie

Proceedings of the 52nd Annual Design Automation Conference, 2015

A network components insertion method for 3D application-specific Network-on-Chip.

RongRong Zhou, Fen Ge, Gui Feng, Ning Wu

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.

Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

A two-phase floorplanning approach for Application-specific Network-on-Chip.

Shuang Yu, Fen Ge, Gui Feng, Ning Wu

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture.

Gui Feng, Fen Ge, Shuang Yu, Ning Wu

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

A Coverage-Driven Verification Platform for Evaluating NoC Performance and Test Structure.

Ying Zhang, Ning Wu, Xiazhi Ke, Fen Ge

Proceedings of the 26th International Conference on Advanced Information Networking and Applications Workshops, 2012

2009

Design of a GALS Wrapper for Network on Chip.

Ning Wu, Fen Ge, Fei Wu

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

A minimum-path mapping algorithm for 2D mesh Network on Chip architecture.

Fen Ge, Ning Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008