Zhengfeng Huang

Orcid: 0000-0001-8695-4478

According to our database1, Zhengfeng Huang authored at least 136 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Reliability analysis and comparison of ring-PUF based on probabilistic models.
Microelectron. J., February, 2024

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers.
ACM Trans. Design Autom. Electr. Syst., January, 2024

A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments.
Microelectron. J., January, 2024

2023
RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.
IEEE Trans. Aerosp. Electron. Syst., December, 2023

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications.
Microelectron. J., September, 2023

Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction.
J. Circuits Syst. Comput., August, 2023

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications.
IEEE Des. Test, August, 2023

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets.
J. Electron. Test., June, 2023

Design of approximate Booth multipliers based on error compensation.
Integr., May, 2023

Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation.
J. Electron. Test., April, 2023

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications.
IEEE Trans. Emerg. Top. Comput., 2023

Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern.
Microelectron. J., 2023

Fault-avoidance C-element based low overhead and TNU-resilient latch.
Microelectron. J., 2023

LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy.
Integr., 2023

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness.
Proceedings of the IEEE International Test Conference in Asia, 2023

A Low Overhead and Double-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of Low-Cost Approximate CMOS Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery.
Proceedings of the 10th International Conference on Dependable Systems and Their Applications, 2023

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A High-Performance and P-Type FeFET-Based Non-Volatile Latch.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments.
IEEE Trans. Emerg. Top. Comput., 2022

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications.
IEEE Trans. Aerosp. Electron. Syst., 2022

M-RO PUF: A portable pure digital RO PUF based on MUX unit.
Microelectron. J., 2022

A reconfigurable PUF structure with dual working modes based on entropy separation model.
Microelectron. J., 2022

RLDA: Valid test pattern identification by machine learning classification method for VLSI test.
Microelectron. J., 2022

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.
J. Circuits Syst. Comput., 2022

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.
Integr., 2022

Valid test pattern identification for VLSI adaptive test.
Integr., 2022

Machine learning classification algorithm for VLSI test cost reduction.
Integr., 2022

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design.
J. Electron. Test., 2022

Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement.
IEEE Des. Test, 2022

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.
Proceedings of the IEEE International Test Conference in Asia, 2022

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021
Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.
IEEE Trans. Emerg. Top. Comput., 2021

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology.
IEEE Trans. Emerg. Top. Comput., 2021

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A high reliability physically unclonable function based on multiple tunable ring oscillator.
Microelectron. J., 2021

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications.
Microelectron. J., 2021

A high-speed and triple-node-upset recovery latch with heterogeneous interconnection.
Microelectron. J., 2021

LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS.
Microelectron. J., 2021

Design of MNU-Resilient latches based on input-split C-elements.
Microelectron. J., 2021

Design of node separated triple-node-upset self-recoverable latch.
Microelectron. J., 2021

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier.
J. Circuits Syst. Comput., 2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.
Integr., 2021

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs.
IEICE Electron. Express, 2021

Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch.
IEEE Access, 2021

Congestion Pattern Prediction for a Busy Traffic Zone Based on the Hidden Markov Model.
IEEE Access, 2021

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

A N: 1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs.
Proceedings of the IEEE International Test Conference in Asia, 2021

Kelvin Bridge Structure Based TSV Test for Weak Faults.
Proceedings of the IEEE International Test Conference in Asia, 2021

TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

GAME: Gaussian Mixture Model Mapping and Navigation Engine on Embedded FPGA.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Architecture of Cobweb-Based Redundant TSV for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.
IEEE Trans. Circuits Syst., 2020

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment.
IEEE Trans. Computers, 2020

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs.
J. Circuits Syst. Comput., 2020

Fault tolerance in memristive crossbar-based neuromorphic computing systems.
Integr., 2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.
IEEE Access, 2020

Jitter-Quantizing-Based TRNG Robust Against PVT Variations.
IEEE Access, 2020

A SEU Immune Flip-Flop with Low Overhead.
Proceedings of the Machine Learning for Cyber Security - Third International Conference, 2020

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

CNN-based Monocular Decentralized SLAM on embedded FPGA.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2019
A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Design of Wireless Network on Chip with Priority-Based MAC.
J. Circuits Syst. Comput., 2019

An enhanced time-to-digital conversion solution for pre-bond TSV dual faults testing.
IEICE Electron. Express, 2019

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets.
IEEE Access, 2019

Temperature-Aware Floorplanning for Fixed-Outline 3D ICs.
IEEE Access, 2019

A Novel Built-In Self-Repair Scheme for 3D Memory.
IEEE Access, 2019

Timetable Coordination of the First Trains for Subway Network With Maximum Passenger Perceived Transfer Quality.
IEEE Access, 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.
Proceedings of the IEEE International Test Conference in Asia, 2019

2018
Design of Low-Power WiNoC with Congestion-Aware Wireless Node.
J. Circuits Syst. Comput., 2018

An improved communication scheme for non-HOL-blocking wireless NoC.
Integr., 2018

Calibration of C-Logit-Based SUE Route Choice Model Using Mobile Phone Data.
Inf., 2018

Research on physical unclonable functions circuit based on three dimensional integrated circuit.
IEICE Electron. Express, 2018

A novel in-field TSV repair method for latent faults.
IEICE Electron. Express, 2018

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.
Proceedings of the IEEE International Test Conference in Asia, 2018

A High Reliability FPGA Chip Identification Generator Based on PDLs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Low-Cost High-Efficiency True Random Number Generator on FPGAs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.
Microelectron. J., 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.
IEICE Trans. Electron., 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.
IEICE Trans. Electron., 2017

A transient pulse dually filterable and online self-recoverable latch.
IEICE Electron. Express, 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.
IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.
IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.
IEICE Electron. Express, 2017

HLDTL: High-performance, low-cost, and double node upset tolerant latch design.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016
An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.
Microelectron. Reliab., 2016

Proactive Control for Oversaturation Mitigation on Evacuation Network: a Multi-Agent Simulation Approach.
Int. J. Comput. Intell. Syst., 2016

Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect.
Proceedings of the International Symposium on Integrated Circuits, 2016

NBTI mitigation by M-IVC with input duty cycle and randomness constraints.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Method of generating strategic guidance information for driving evacuation flows to approach safety-based system optimal dynamic flows: Case study of a large stadium.
J. Syst. Sci. Complex., 2015

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.
IEICE Trans. Electron., 2015

A High Performance SEU Tolerant Latch.
J. Electron. Test., 2015

MTTF-Aware Reliability Task Scheduling for Heterogeneous Multicore System.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014
A high performance SEU-tolerant latch for nanoscale CMOS technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design of a Radiation Hardened Latch for Low-Power Circuits.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
The Optimal Taxi Fleet Size Structure under Various Market Regimes When Charging Taxis with Link-Based Toll.
J. Appl. Math., 2013

A dynamic self-adaptive correction method for error resilient application.
Proceedings of the Design, Automation and Test in Europe, 2013

2010
A scheme of test data compression based on coding of even bits marking and selective output inversion.
Comput. Electr. Eng., 2010

2008
Balancing wrapper chains of SoC core based on best interchange decreasing.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
Test data compression scheme based on variable-to-fixed-plus-variable-length coding.
J. Syst. Archit., 2007

A Novel Collaborative Scheme of Test Data Compression Based on Fixed-Plus-variable-Length Coding.
Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

2005
A New Algorithm for Reducing Communication Cost of Time-dependent Monte Carlo Transport.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

2004
Application of MPI-IO in Parallel Particle Transport Monte-Carlo Simulation.
Parallel Algorithms Appl., 2004

2003
The Parallel Communication of Time-Dependent Monte Carlo Transport.
Proceedings of the 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 2003


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