Xingzhou Cheng

Orcid: 0000-0001-7623-2033

According to our database1, Xingzhou Cheng authored at least 6 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.
Sci. China Inf. Sci., April, 2023

2022
S<sup>2</sup> Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.
IEEE Trans. Computers, 2022

2021
S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.
CoRR, 2021

2020
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2016
A unified OLAP/OLTP big data processing framework in telecom industry.
Proceedings of the 16th International Symposium on Communications and Information Technologies, 2016


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