Chao Wang
Orcid: 0000-0002-7460-7628Affiliations:
- Huazhong University of Science and Technology, School of Optical and Electronic Information, Wuhan, China
- Nanyang Technological University, Singapore (PhD 2008)
According to our database1,
Chao Wang
authored at least 37 papers
between 2019 and 2023.
Collaborative distances:
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Bibliography
2023
Deep convolutional transfer learning-based structural damage detection with domain adaptation.
Appl. Intell., March, 2023
A Reconfigurable Coprocessor for Simultaneous Localization and Mapping Algorithms in FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
An Energy-Efficient, Resource-Efficient and High Frame-Rate End-to-End Pedestrian Detector Using HOG-SVM for Intelligent Edge Devices.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
A High-Linearity, Energy-Efficient Switched-Capacitor Computing Circuit for Edge Applications.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
INVITED PAPER: Challenges and Trends of Memristive IMPLY-based In-memory Computing: Efficiency, Reliability, and Compatibility Perspectives.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A Reconfigurable High-Precision and Energy-Efficient Circuit Design of Sigmoid, Tanh and Softmax Activation Functions.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A Novel Transpose 2T-DRAM based Computing-in-Memory Architecture for On-chip DNN Training and Inference.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
In Situ Aging-Aware Error Monitoring Scheme for IMPLY-Based Memristive Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation.
IEEE Trans. Biomed. Circuits Syst., 2022
Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices.
Sensors, 2022
Efficient Hardware Accelerator Design of Non-Linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM for Mobile Robots.
Sensors, 2022
Robust finite-time asynchronous control for nonlinear Markov jump systems with partial mode information and random packet loss.
J. Frankl. Inst., 2022
Entropy Sources Based on Silicon Chips: True Random Number Generator and Physical Unclonable Function.
Entropy, 2022
Automatic pulmonary auscultation grading diagnosis of Coronavirus Disease 2019 in China with artificial intelligence algorithms: A cohort study.
Comput. Methods Programs Biomed., 2022
Multi-dimensional recurrent neural network for remaining useful life prediction under variable operating conditions and multiple fault modes.
Appl. Soft Comput., 2022
Energy-Efficient Intelligent Pulmonary Auscultation for Post COVID-19 Era Wearable Monitoring Enabled by Two-Stage Hybrid Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
An IMPLY-based Memristive Multiplier for Computing-in-Memory Systems with Weight-Stationary CNN Acceleration.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A Novel Fold-Back Current Limiting Protection used in Sub-threshold LDO for Wireless Sensor Applications.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the IEEE International Conference on Real-time Computing and Robotics, 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Novel Area-Efficient Fast CORDIC for Energy-efficient Adaptive Exponential Integrate and Fire Neuron Design.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
An energy-efficient and high-PSNR image denoising pre-processor based on optimized non-local means algorithm for real-time FHD video applications.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Data Non-destructive IMPLY-based Memristive Semi-parallel Full-Adder for Computing-in-memory Systems.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices.
Sensors, 2020
Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor.
Microelectron. J., 2020
An Ultra-low Power Relaxation Oscillator with Novel Ultra-low Leakage Switch and Temperature-compensated Resistor.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A Novel Variation-aware Error Monitoring Scheme for Memristor-based Material Implication Logic.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019