Yazheng Tu

Orcid: 0000-0002-1624-9500

According to our database1, Yazheng Tu authored at least 11 papers between 2022 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication.
IEEE Comput. Archit. Lett., 2023

LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator.
IEEE Comput. Archit. Lett., 2022

Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

HPMA-Saber: High-Performance Polynomial Multiplication Accelerator for KEM Saber.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022


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