Ujjwal Guin

According to our database1, Ujjwal Guin authored at least 60 papers between 2011 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Complexity Analysis of the SAT Attack on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking.
IEEE Trans. Computers, August, 2023

On-Demand Device Authentication using Zero-Knowledge Proofs for Smart Systems.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Test and Yield Loss Reduction of AI and Deep Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking.
J. Electron. Test., 2022

A Systematic Bit Selection Method for Robust SRAM PUFs.
J. Electron. Test., 2022

Beware of Discarding Used SRAMs: Information is Stored Permanently.
CoRR, 2022

AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking.
CoRR, 2022

Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator.
IEEE Comput. Archit. Lett., 2022

Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Chosen-Plaintext Attack on Energy-Efficient Hardware Implementation of GIFT-COFB.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

CamSkyGate: camouflaged skyrmion gates for protecting ICs.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
TAAL: Tampering Attack on Any Key-based Logic Locked Circuits.
ACM Trans. Design Autom. Electr. Syst., 2021

A novel topology-guided attack and its countermeasure towards secure logic locking.
J. Cryptogr. Eng., 2021

Estimating Operational Age of an Integrated Circuit.
J. Electron. Test., 2021

Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Special Session: Reliability Analysis for ML/AI Hardware.
CoRR, 2021

Defect Characterization and Testing of Skyrmion-Based Logic Circuits.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Special Session: Reliability Analysis for AI/ML Hardware.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Survey of Recent Developments for Hardware Trojan Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Blockchain-based Contactless Delivery System for Addressing COVID-19 and Other Pandemics.
Proceedings of the 2021 IEEE International Conference on Blockchain, 2021

2020
End-to-End Traceability of ICs in Component Supply Chain for Fighting Against Recycling.
IEEE Trans. Inf. Forensics Secur., 2020

Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices.
J. Electron. Test., 2020

A Robust, Low-Cost and Secure Authentication Scheme for IoT Applications.
Cryptogr., 2020

ATPG-Guided Fault Injection Attacks on Logic Locking.
CoRR, 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

Yield Loss Reduction and Test of AI and Deep Learning Accelerators.
CoRR, 2020

Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session: Novel Attacks on Logic-Locking.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

A Novel Tampering Attack on AES Cores with Hardware Trojans.
Proceedings of the IEEE International Test Conference in Asia, 2020

2019
Standards for Hardware Security.
GetMobile Mob. Comput. Commun., 2019

Blockchain in IoT: Current Trends, Challenges, and Future Roadmap.
J. Hardw. Syst. Secur., 2019

Low-Cost and Secure Firmware Obfuscation Method for Protecting Electronic Systems From Cloning.
IEEE Internet Things J., 2019

A Blockchain-Based Framework for Supply Chain Provenance.
IEEE Access, 2019

Special Session: Delay Fault Testing - Present and Future.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Two-Pattern ∆IDDQ Test for Recycled IC Detection.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Countering Botnet of Things using Blockchain-Based Authenticity Framework.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

TGA: An Oracle-less and Topology-Guided Attack on Logic Locking.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Modeling and test generation for combinational hardware Trojans.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Ensuring Proof-of-Authenticity of IoT Edge Devices Using Blockchain Technology.
Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018

Robust, low-cost, and accurate detection of recycled ICs using digital signatures.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware.
IEEE Trans. Dependable Secur. Comput., 2017

TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era.
J. Hardw. Syst. Secur., 2017

A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016
Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling.
IEEE Trans. Very Large Scale Integr. Syst., 2016

FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs.
ACM Trans. Design Autom. Electr. Syst., 2016

2015
Performance optimization for on-chip sensors to detect recycled ICs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.
Proc. IEEE, 2014

A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment.
J. Electron. Test., 2014

Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead.
J. Electron. Test., 2014

Low-cost On-Chip Structures for Combating Die and IC Recycling.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Anti-counterfeit Techniques: From Design to Resign.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Functional Fmax test-time reduction using novel DFTs for circuit initialization.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2011
Design for Bit Error Rate estimation of high speed serial links.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011


  Loading...