Angela Krstic

According to our database1, Angela Krstic authored at least 37 papers between 1995 and 2004.

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Bibliography

2004
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs.
IEEE Des. Test Comput., 2004

2003
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Diagnosis of Delay Defects Using Statistical Timing Models.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

On Structural vs. Functional Testing for Delay Faults.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.
Proceedings of the 2003 Design, 2003

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
Proceedings of the 40th Design Automation Conference, 2003

Experience in critical path selection for deep sub-micron delay test and timing validation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Embedded Software-Based Self-Test for Programmable Core-Based Designs.
IEEE Des. Test Comput., 2002

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation.
Proceedings of the 39th Design Automation Conference, 2002

Embedded software-based self-testing for SoC design.
Proceedings of the 39th Design Automation Conference, 2002

2001
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Delay testing considering crosstalk-induced effects.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Fast Statistical Timing Analysis By Probabilistic Event Propagation.
Proceedings of the 38th Design Automation Conference, 2001

2000
Estimation for maximum instantaneous current through supply lines for CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Testable Path Delay Fault Cover for Sequential Circuits.
J. Inf. Sci. Eng., 2000

Functionally Testable Path Delay Faults on a Microprocessor.
IEEE Des. Test Comput., 2000

On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Test program synthesis for path delay faults in microprocessor cores.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Dynamic Timing Analysis Considering Power Supply Noise Effects.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Performance sensitivity analysis using statistical method and its applications to delay.
Proceedings of ASP-DAC 2000, 2000

1999
Primitive delay faults: identification, testing, and design for testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Current Directions in Automatic Test-Pattern Generation.
Computer, 1999

Testing High Speed VLSI Devices Using Slower Testers.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Delay testing considering power supply noise effects.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.
J. Electron. Test., 1997

Design for Primitive Delay Fault Testability.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits.
Proceedings of the 34st Conference on Design Automation, 1997

Post-Layout Logic Restructuring for Performance Optimization.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Generation of High Quality Tests for Robustly Untestable Path Delay Faults.
IEEE Trans. Computers, 1996

Identification and Test Generation for Primitive Faults.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Generation of high quality tests for functional sensitizable paths.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995


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