Yichao Zhang

According to our database, Yichao Zhang authored at least 13 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks.

Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.

Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini

CoRR, July, 2025

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.

Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini

IEEE J. Solid State Circuits, April, 2025

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster.

Sergio Mazzola, Yichao Zhang, Marco Bertuletti, Diyou Shen, Luca Benini

CoRR, April, 2025

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.

Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini

CoRR, January, 2025

TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs.

Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024

A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR.

Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini

CoRR, 2024

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.

Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.

Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication.

Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.

Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor.

Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.

Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022