Matheus A. Cavalcante
Orcid: 0000-0001-9199-1708
According to our database1,
Matheus A. Cavalcante
authored at least 27 papers
between 2016 and 2024.
Collaborative distances:
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Bibliography
2024
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication.
CoRR, 2024
2023
IEEE Trans. Computers, December, 2023
IEEE Des. Test, December, 2023
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor.
CoRR, 2023
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.
CoRR, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Trans. Computers, 2022
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
2019
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI.
CoRR, 2019
2018
Evolutionary Multiobjective Strategy for Regenerator Placement in Elastic Optical Networks.
IEEE Trans. Commun., 2018
Optimizing the cost function of power series routing algorithm for transparent elastic optical networks.
Opt. Switch. Netw., 2018
2017
SimEON: an open-source elastic optical network simulator for academic and industrial purposes.
Photonic Netw. Commun., 2017
2016
A case study of regenerator placement and regenerator assignment in dynamic translucent elastic optical networks.
Proceedings of the 18th International Conference on Transparent Optical Networks, 2016