Marco Bertuletti

According to our database, Marco Bertuletti authored at least 21 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling.

Yinrong Li, Zexin Fu, Yichao Zhang, Germain Haugou, Chi Zhang, Marco Bertuletti, Bowen Wang, Luca Benini

CoRR, May, 2026

TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks.

Marco Bertuletti, Yichao Zhang, Diyou Shen, Alessandro Vanelli-Coralli, Frank K. Gürkaynak, Luca Benini

CoRR, April, 2026

A Low-Power 1.2 TFLOPS/W Merge-Split RVV Processor for Mixed Scalar-Vector Workloads.

Mattia Sinigaglia, Marco Bertuletti, Gianmarco Ottavi, Amirhossein Kiamarzi, Matteo Perotti, Giuseppe Tagliavini, Luca Benini, Davide Rossi

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing.

Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti, Luigi Ghionda, Mattia Orlandi, Riccardo Tedeschi, Aurora Di Giampietro, Yvan Tortorella, Luca Bertaccini, Simone Benatti, Giuseppe Tagliavini, Luca Benini, Francesco Conti, Davide Rossi

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link.

Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini

IEEE Trans. Computers, November, 2025

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN.

Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, Luca Benini

CoRR, September, 2025

A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks.

Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster.

Sergio Mazzola, Yichao Zhang, Marco Bertuletti, Diyou Shen, Luca Benini

CoRR, April, 2025

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC.

Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.

Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini

Proceedings of the 10th International Workshop on Advances in Sensors and Interfaces, 2025

TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters.

Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

A Compute&Memory Efficient Model-Driven Neural 5G Receiver for Edge AI-assisted RAN.

Mahdi Abdollahpour, Marco Bertuletti, Yichao Zhang, Yawei Li, Luca Benini, Alessandro Vanelli-Coralli

Proceedings of the 2025 IEEE Global Communications Conference, 2025

TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs.

Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference, 2025

Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks.

Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications.

Danilo Cammarata, Matteo Perotti, Marco Bertuletti, Angelo Garofalo, Pasquale Davide Schiavone, David Atienza, Luca Benini

Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2025

A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-Core RV Clusters for Attention-Based Model Deployment.

Bowen Wang, Marco Bertuletti, Yichao Zhang, Victor J. B. Jung, Luca Benini

Proceedings of the 36th IEEE International Conference on Application-specific Systems, 2025

2024

A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR.

Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini

CoRR, 2024

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.

Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.

Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023

Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.

Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor.

Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023