Yiqiao Liao

According to our database1, Yiqiao Liao authored at least 11 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
KwaiYiiMath: Technical Report.
CoRR, 2023

Privacy-Preserving DNN Training with Prefetched Meta-Keys on Heterogeneous Neural Network Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Social Bias Meets Data Bias: The Impacts of Labeling and Measurement Errors on Fairness Criteria.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
Multichannel Multidomain-Based Knowledge Distillation Algorithm for Sleep Staging With Single-Channel EEG.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

LightSleepNet: Design of a Personalized Portable Sleep Staging System Based on Single-Channel EEG.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Persia: An Open, Hybrid System Scaling Deep Learning-based Recommenders up to 100 Trillion Parameters.
Proceedings of the KDD '22: The 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, Washington, DC, USA, August 14, 2022

2020
Design of a Hybrid Competition-Cooperation Teacher-Students Model for Single Channel Based Sleep Staging.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Tri-FeatureNet: An Adversarial Learning-Based Invariant Feature Extraction for Sleep Staging using Single-Channel EEG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Design of a Flexible Wearable Smart sEMG Recorder Integrated Gradient Boosting Decision Tree Based Hand Gesture Recognition.
IEEE Trans. Biomed. Circuits Syst., 2019

2018
Design and FPGA Implementation of an High Efficient XGBoost Based Sleep Staging Algorithm Using Single Channel EEG.
Proceedings of the Cognitive Systems and Signal Processing - 4th International Conference, 2018

2017
Design of a closed-loop, bi-directional brain-machine-interface integrated on-chip spike sorting.
Proceedings of the 12th IEEE International Conference on ASIC, 2017


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