Jin Ouyang

According to our database1, Jin Ouyang authored at least 19 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Perph: A Workload Co-location Agent with Online Performance Prediction and Resource Inference.
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2019
Perphon: a ML-based Agent for Workload Co-location via Performance Prediction and Resource Inference.
Proceedings of the ACM Symposium on Cloud Computing, SoCC 2019, 2019

2017
Reliable Computing Service in Massive-Scale Systems through Rapid Low-Cost Failover.
IEEE Trans. Serv. Comput., 2017

2016
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
DimNoC: a dim silicon approach towards power-efficient on-chip network.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
Designing energy-efficient NoC for real-time embedded systems through slack optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

SDGP: A developmental approach for traveling salesman problems.
Proceedings of the IEEE Symposium on Computational Intelligence In Production And Logistics Systems, 2013

2011
Three-dimensional Integrated Circuits: Design, EDA, and Architecture.
Found. Trends Electron. Des. Autom., 2011

F<sup>2</sup>BFLY: an on-chip free-space optical network with wavelength-switching.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

A frequent-value based PRAM memory architecture.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Enabling quality-of-service in nanophotonic network-on-chip.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.
Proceedings of the 2009 International Conference on Compilers, 2009

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Arithmetic unit design using 180nm TSV-based 3D stacking technology.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Power optimization for FinFET-based circuits using genetic algorithms.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

ILP-based scheme for timing variation-aware scheduling and resource binding.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008


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