Yoshiji Kobayashi

According to our database, Yoshiji Kobayashi authored at least 6 papers between 1986 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing.

Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino

IEEE J. Solid State Circuits, 1998

1997

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic.

Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino

IEEE J. Solid State Circuits, 1997

1995

3.5-Gb/s⨉4-ch Si bipolar LSI's for optical interconnections.

Noboru Ishihara, Shuichi Fujita, Minoru Togashi, Shigeki Hino, Yoshimitsu Arai, Nobuyuki Tanaka, Yoshiji Kobayashi, Yukio Akazawa

IEEE J. Solid State Circuits, December, 1995

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops.

Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi

IEEE J. Solid State Circuits, January, 1995

1994

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology.

Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi

IEEE J. Solid State Circuits, May, 1994

1986

A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit.

Yousuke Yamamoto, Hiroshi Miyanaga, Yoshiji Kobayashi, Yasukazu Terada, Naoaki Yamanaka

IEEE Trans. Commun., 1986