Yoshio Kameda

Orcid: 0009-0004-5344-6046

According to our database1, Yoshio Kameda authored at least 10 papers between 1996 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Method of Identifying Causes of Prediction Errors to Accelerate MLOps.
Proceedings of the IEEE/ACM International Workshop on Deep Learning for Testing and Testing for Deep Learning, 2023

Quantitative Decomposition of Prediction Errors Revealing Multi-Cause Impacts: An Insightful Framework for MLOps.
Proceedings of the 32nd ACM International Conference on Information and Knowledge Management, 2023

2018
A Rare and Critical Condition Search Technique and its Application to Telescope Stray Light Analysis.
Proceedings of the 2018 SIAM International Conference on Data Mining, 2018

2010
Gate-oxide early-life failure identification using delay shifts.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2008
Design and Demonstration of a 4×4 SFQ Network Switch Prototype System and 10-Gbps Bit-Error-Rate Measurement.
IEICE Trans. Electron., 2008

Development of Cryopackaging and I/O Technologies for High-Speed Superconductive Digital Systems.
IEICE Trans. Electron., 2008

2005
Development of Passive Interconnection Technology for SFQ Circuits.
IEICE Trans. Electron., 2005

1998
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1996
Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996


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