Stanislav Polonsky

According to our database, Stanislav Polonsky authored at least 4 papers between 1997 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.

Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia N. Sanda

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA).

William V. Huott, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Dennis Manzer, Pia N. Sanda, Steve Wilson, Yuen H. Chan, Antonio Pelella, Stanislav Polonsky

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.

Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya

Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997

Delay Insensitive Logic for RSFQ Superconductor Technology.

Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell

Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997