Yoshitaka Murasaka

According to our database, Yoshitaka Murasaka authored at least 12 papers between 2001 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging.

Takamaro Kikkawa, Yoshihiro Masui, Akihiro Toya, Hiroyuki Ito, Takuichi Hirano, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Tsuyoshi Matsumaru, Michimasa Yamaguchi, Mitsutoshi Sugawara, Afreen Azhari, Hang Song, Shinsuke Sasada, Atsushi Iwata

IEEE Trans. Biomed. Circuits Syst., 2020

2019

Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection.

Akihiro Toya, Takamaro Kikkawa, Yoshihiro Masui, Mitsutoshi Sugawara, Hiroyuki Ito, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Atsushi Iwata

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018

Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection.

Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017

Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system.

Akihiro Toya, Yoshihiro Masui, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Differential equivalent time sampling receiver for breast cancer detection.

Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2011

Background Calibration Techniques for Low-Power and High-Speed Data Conversion.

Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto

IEICE Trans. Electron., 2011

2007

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications.

Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation.

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2002

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.

Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.

Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001