Atsuki Inoue

According to our database1, Atsuki Inoue authored at least 16 papers between 2006 and 2021.

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Bibliography

2021
A High-Speed Neural Architecture Search Considering the Number of Weights.
Proceedings of the KI 2021: Advances in Artificial Intelligence - 44th German Conference on AI, Virtual Event, September 27, 2021

Real-time concentration measurement through forehead cerebral blood flow dynamics using NIRS.
Proceedings of the 9th International Winter Conference on Brain-Computer Interface, 2021

Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization.
Proceedings of the Asian Conference on Machine Learning, 2021

2019
Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design.
Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2019

2018
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning.
Proceedings of the 27th IEEE International Workshop on Machine Learning for Signal Processing, 2017

Session 20 overview: Digital voltage regulators and low-power techniques.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
ES2: Computing architectures paving the path to power efficiency.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Session 4 overview: Processors: High-performance digital subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
Session 14 overview: Digital PLLs and building blocks.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Vision for future television.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Comparison between power gating and DVFS from the viewpoint of energy efficiency.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Design constraint of fine grain supply voltage control LSI.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2009
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support.
IEEE J. Solid State Circuits, 2009

2007
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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