Yu Yang

According to our database, Yu Yang authored at least 21 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

Scalable Multi-FPGA HPC Architecture for Associative Memory System.

Deyu Wang, Xiaoze Yan, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou

IEEE Trans. Biomed. Circuits Syst., April, 2025

Modeling and Scheduling of Composable Instruction Set.

Yu Yang, Paul Delestrac, Ahmed Hemani

Proceedings of the 28th Euromicro Conference on Digital System Design, 2025

2024

Automating functional unit and register binding for synchoros CGRA platform.

Pudi Dhilleswararao, Utsav Tiwari, Srinivas Boppu, Yu Yang, Ahmed Hemani

Des. Autom. Embed. Syst., June, 2024

CIS: Composable Instruction Set for Streaming Applications: Design, Modeling, and Scheduling.

Yu Yang, Jordi Altayó González, Ahmed Hemani

CoRR, 2024

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study.

Pudi Dhilleswararao, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi

IEEE Access, 2024

Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework.

Pudi Dhilleswararao, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi

IEEE Access, 2024

Exploration of Custom Floating-Point Formats: A Systematic Approach.

Saba Yousefzadeh, Yu Yang, Astile Peter, Dimitrios Stathis, Ahmed Hemani

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

FPGA-Based HPC for Associative Memory System.

Deyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures.

Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani

Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

2022

Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style.

Yu Yang, Ahmed Hemani

CoRR, 2022

Reducing the Configuration Overhead of the Distributed Two-level Control System.

Yu Yang, Dimitrios Stathis, Ahmed Hemani

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Design and Implementation of Optimized Register File for Streaming Applications.

Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Scheduling Persistent and Fully Cooperative Instructions.

Yu Yang, Ahmed Hemani, Kolin Paul

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex.

Dimitrios Stathis, Yu Yang, Ahmed Hemani, Anders Lansner

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation.

Jiawei Xu, Deyu Wang, Feng Li, Lianhao Zhang, Dimitrios Stathis, Yu Yang, Yi Jin, Anders Lansner, Ahmed Hemani, Zhuo Zou, Li-Rong Zheng

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.

Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn

J. Signal Process. Syst., 2020

A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network.

Lizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2019

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.

Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn

CoRR, 2019

Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps.

Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred G. Grabherr, Rafi Ahmad

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform.

Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred G. Grabherr, Rafi Ahmad

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

2017

MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs.

Yu Yang, Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis

Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017