Srinivas Boppu

According to our database, Srinivas Boppu authored at least 23 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction.

Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi

ACM Trans. Design Autom. Electr. Syst., 2023

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT.

Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Implementation of Image Averaging on DRRA and DiMArch Architectures.

Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures.

Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani

Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

Compressive Sensing-Based Automatic PPG Signal Quality Assessment Using CNN for Energy-Constrained Medical Devices.

Yalagala Sivanjaneyulu, Srinivas Boppu, M. Sabarimalai Manikandan

Proceedings of the 15th International Conference on Electronics, 2023

Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures.

Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey.

Pudi Dhilleswararao, Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi

IEEE Access, 2022

Efficient Hardware Architecture for Posit Addition/Subtraction.

Susheel Ujwal Siddamshetty, Srinivas Boppu, Debapratim Ghosh

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization.

Ashish Reddy Bommana, Srinivas Boppu

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Hand Gesture Recognition System in the Complex Background for Edge Computing Devices.

Chakkapalli Manikanta Suryateja, Srinivas Boppu, Linga Reddy Cenkeramaddi, Barathram Ramkumar

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Efficient Multiplication and Accumulation of Signed Numbers.

Susheel Ujwal Siddamshetty, Suresh Nambi, Srinivas Boppu, Debapratim Ghosh

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

Design and Implementation of Optimized Register File for Streaming Applications.

Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020

Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats.

Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Design of a Real-Time Automatic Source Monitoring Framework Based on Sound Source Localization.

Spandan Dey, Srinivas Boppu, M. Sabarimalai Manikandan

Proceedings of the 7th International Conference on Digital Information Processing and Communications, 2019

2015

Code Generation for Tightly Coupled Processor Arrays.

Srinivas Boppu

PhD thesis, 2015

2014

Compact Code Generation for Tightly-Coupled Processor Arrays.

Srinivas Boppu, Frank Hannig, Jürgen Teich

J. Signal Process. Syst., 2014

Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach.

Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche

ACM Trans. Embed. Comput. Syst., 2014

2013

System integration of tightly-coupled processor arrays using reconfigurable buffer structures.

Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich

Proceedings of the Computing Frontiers Conference, 2013

Loop program mapping and compact code generation for programmable hardware accelerators.

Srinivas Boppu, Frank Hannig, Jürgen Teich

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Hierarchical power management for adaptive tightly-coupled processor arrays.

Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich

ACM Trans. Design Autom. Electr. Syst., 2012

A prototype of an invasive tightly-coupled processor array.

Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Design of Low Power On-chip Processor Arrays.

Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.

Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011