Yuan-Ho Chen
Orcid: 0000-0001-5651-7584
According to our database1,
Yuan-Ho Chen
authored at least 43 papers
between 2006 and 2024.
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Bibliography
2024
A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN).
IEEE Access, 2024
2023
Proceedings of the 20th International SoC Design Conference, 2023
Hybrid CNN-LSTM Network for ECG Classification and Its Software-Hardware Co-Design Approach.
Proceedings of the 20th International SoC Design Conference, 2023
2022
A VLSI Chip for the Abnormal Heart Beat Detection Using Convolutional Neural Network.
Sensors, 2022
Very Large-Scale Integration for Premature Ventricular Contraction Detection Using a Convolutional Neural Network.
J. Circuits Syst. Comput., 2022
IEEE Access, 2022
Very-large-scale Integration of a Dual-lead Electrocardiogram Compression Chip with Modified Huffman Encoding.
Proceedings of the 4th IEEE Global Conference on Life Sciences and Technologies, 2022
Proceedings of the 19th International SoC Design Conference, 2022
2021
Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Simple and hardware-efficient row-based direct-mapping estimators in fixed-width modified Booth multipliers.
Int. J. Circuit Theory Appl., 2021
2020
Low-Cost Implementation of Independent Component Analysis for Biomedical Signal Separation Using Very-Large-Scale Integration.
IEEE Trans. Circuits Syst., 2020
A VLSI Implementation of Independent Component Analysis for Biomedical Signal Separation Using CORDIC Engine.
IEEE Trans. Biomed. Circuits Syst., 2020
A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture.
EURASIP J. Adv. Signal Process., 2020
VLSI Implementation of a Cost-Efficient 3-Lead Lossless ECG Compressor and Decompressor.
Circuits Syst. Signal Process., 2020
Premature Ventricular Complex Detection Chip Obtained Using Convolution Neural Network.
Proceedings of the 2020 International Conference on Artificial Intelligence in Information and Communication, 2020
2019
Run-time calibration scheme for the implementation of a robust field-programmable gate array-based time-to-digital converter.
Int. J. Circuit Theory Appl., 2019
EURASIP J. Adv. Signal Process., 2019
2018
Fine-Tuning Accuracy Using Conditional Probability of the Bottom Sign-Bit in Fixed-Width Modified Booth Multiplier.
Circuits Syst. Signal Process., 2018
Multiple Leads With a Switch Mode for Lossless and Lossy Compression Using Very-Large-Scale Integration Technology.
IEEE Access, 2018
2017
Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation.
Sensors, 2017
Int. J. Circuit Theory Appl., 2017
2016
Int. J. Circuit Theory Appl., 2016
Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series.
Circuits Syst. Signal Process., 2016
2015
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing.
Sensors, 2015
2014
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst., 2014
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique.
J. Circuits Syst. Comput., 2014
J. Circuits Syst. Comput., 2014
Ind. Manag. Data Syst., 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Appl. Soft Comput., 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
2006
IEEE Trans. Wirel. Commun., 2006
IEEE Trans. Signal Process., 2006
Proceedings of the IEEE International Conference on Systems, 2006