Tsin-Yuan Chang

According to our database1, Tsin-Yuan Chang authored at least 36 papers between 1988 and 2019.

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Bibliography

2019
A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display.
IEEE J. Solid State Circuits, 2019

2014
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy.
IEEE Trans. Very Large Scale Integr. Syst., 2014

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems.
IEEE J. Solid State Circuits, 2012

2011
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

2010
A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009
IEEE Standard 1500 Compatible Delay Test Framework.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A current mode adaptive on-time control scheme for fast transient DC-DC converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006
A chaos-based pseudo random number generator using timing-based reseeding method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range.
Proceedings of the 15th Asian Test Symposium, 2006

2005
On-chip accumulated jitter measurement for phase-locked loops.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Built-In Parametric Timing Measurement Unit.
IEEE Des. Test Comput., 2004

A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Timing measurement unit with multi-stage TVC for embedded memories.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
An Access Timing Measurement Unit of Embedded Memory.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
A built-in timing parametric measurement unit.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A low-cost CMOS time interval measurement core.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
A realistic fault model for flash memories.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

SoC Testing and P1500 Standard.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
A Programmable BIST Core for Embedded DRAM.
IEEE Des. Test Comput., 1999

1992
A design for concurrent error detections in FPLAs.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1990
An efficient output phase assignment for PLA minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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