Yue Lu
Affiliations:- Qualcomm Atheros Inc., San Jose, CA, USA
- University of California, Berkeley, CA, USA (Ph.D.)
According to our database1,
Yue Lu
authored at least 10 papers
between 2011 and 2017.
Collaborative distances:
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Bibliography
2017
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2017
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2016
2015
Proceedings of the Symposium on VLSI Circuits, 2015
2013
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters.
IEEE J. Solid State Circuits, 2013
Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
BAG: a designer-oriented integrated framework for the development of AMS circuit generators.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011