Nathan Narevsky

According to our database1, Nathan Narevsky authored at least 19 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
An Automated and Process-Portable Generator for Phase-Locked Loop.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2019
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.
IEEE J. Solid State Circuits, 2019

A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

BAG: A Process-Portable Framework for Generator-based AMS Circuit Design.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018

An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

BAG2: A process-portable framework for generator-based AMS circuit design.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018


2016
Design of Energy- and Cost-Efficient Massive MIMO Arrays.
Proc. IEEE, 2016

2015
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation.
IEEE J. Solid State Circuits, 2015

A scalable massive MIMO array architecture based on common modules.
Proceedings of the IEEE International Conference on Communication, 2015

2014
Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver.
IEEE J. Solid State Circuits, 2014

A 4.78mm<sup>2</sup> fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A Fully-Integrated, Miniaturized (0.125 mm<sup>2</sup>) 10.5 µW Wireless Neural Sensor.
IEEE J. Solid State Circuits, 2013

A mixed-signal 32-coefficient RX-FFE 100-coefficient DFE for an 8Gb/s 60GHz receiver in 65nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

BAG: a designer-oriented integrated framework for the development of AMS circuit generators.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
A fully-integrated 10.5µW miniaturized (0.125mm<sup>2</sup>) wireless neural sensor.
Proceedings of the Symposium on VLSI Circuits, 2012


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