Yuejian Wu

According to our database1, Yuejian Wu authored at least 24 papers between 1992 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2012
"Free" Razor: A novel adaptive voltage scaling low power technique for data path SoC designs.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2008
Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2006
Fast detection of data retention faults and other SRAM cell open defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low Power SoC Memory BIST.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs.
Proceedings of the 2005 Design, 2005

A retention-aware test power model for embedded SRAM.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Low power decoding of BCH codes.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Designs for Reducing Test Time of Distributed Small Embedded SRAMs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Testing ASICs with multiple identical cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001
Shadow write and read for at-speed BIST of TDM SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1999
Scan-based BIST fault diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Interconnect delay fault testing with IEEE 1149.1.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Diagnosis of Scan Chain Failures.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Built-In Self-Test for Multi-Port RAMs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
BIST Fault Diagnosis in Scan-Based VLSI Environments.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST.
IEEE Trans. Computers, 1995

Reducing Hardware with Fuzzy Multiple Signature Analysis.
IEEE Des. Test Comput., 1995

1993
Minimal hardware multiple signature analysis for BIST.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Acceleration of back propagation through initial weight pre-training with delta rule.
Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

1992
Accelerated path delay fault simulation.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992


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