Ahmed Elmallah

Orcid: 0000-0002-0285-9957

According to our database1, Ahmed Elmallah authored at least 17 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 3.2-GHz 405 fs<sub>rms</sub> Jitter -237.2 dB FoM<sub>JIT</sub> Ring-Based Fractional-N Synthesizer.
IEEE J. Solid State Circuits, 2022

2021
A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
Circuits for time-domain signal processing
PhD thesis, 2020

3.2 A 0.0088mm<sup>2</sup> Resistor-Based Temperature Sensor Achieving 92fJ·K<sup>2</sup> FoM in 65nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers.
IEEE J. Solid State Circuits, 2019

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.
IEEE J. Solid State Circuits, 2019

2018
A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier.
IEEE J. Solid State Circuits, 2018

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 0.7V time-based inductor for fully integrated low bandwidth filter applications.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2011
A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floor.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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