Yushen Fu

According to our database, Yushen Fu authored at least 7 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging.

Yushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun, Xueqing Li, Huazhong Yang

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations.

Yiming Chen, Yushen Fu, Mingyen Lee, Sumitha George, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration.

Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li, Huazhong Yang

IEEE Trans. Very Large Scale Integr. Syst., February, 2023

2022

FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications.

Yiming Chen, Yushen Fu, Mingyen Lee, Sumitha George, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li

CoRR, 2022

2021

Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs.

Yang Liu, Yushen Fu, Chengyu Huang, Huazhong Yang, Xueqing Li

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching.

Chengyu Huang, Yushen Fu, Zekun Yang, Yang Liu, Nan Sun, Xueqing Li, Huazhong Yang

Proceedings of the 47th ESSCIRC 2021, 2021

2019

Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs.

Longqiang Lai, Xueqing Li, Yushen Fu, Yongpan Liu, Huazhong Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2019