Zhicong Luo

Orcid: 0000-0001-6008-3897

According to our database1, Zhicong Luo authored at least 19 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Lightweight and High-Precision Passion Fruit YOLO Detection Model for Deployment in Embedded Devices.
Sensors, August, 2024

A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-μm CMOS process.
Integr., January, 2024

A -184 dB PSRR and 2.47 μVrms noise self biased bandgap reference based on FVF structure.
Microelectron. J., 2024

A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS Technology.
Integr., 2024

2023
A 25-Gb/s dual-loop adaptive continuous-time linear equalizer based on power comparison for the optical transmitter.
Microelectron. J., September, 2023

A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

A 1.2-V 0.959-ppm/°C multi-section curvature-compensated bandgap voltage reference with trimming.
Microelectron. J., 2023

A rail-to-rail high speed continuous time comparator for ToF application.
IEICE Electron. Express, 2023

Threshold-programmable loss-of-signal detection circuit with temperature compensation.
IEICE Electron. Express, 2023

2022
TripleRE: Knowledge Graph Embeddings via Tripled Relation Vectors.
CoRR, 2022

2021
A 1.2-V 2.18-ppm/°C curvature-compensated CMOS bandgap reference.
IEICE Electron. Express, 2021

2020
A 25-Gb/s high-sensitivity transimpedance amplifier with bandwidth enhancement.
IEICE Electron. Express, 2020

2019
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2018

A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst., 2017

2016
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst., 2016

Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016


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