Tzu-Yi Yang

According to our database1, Tzu-Yi Yang authored at least 19 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.
IEEE Trans. Biomed. Eng., 2019

2018
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2018

2017
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst., 2017

2015
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.
IEEE J. Solid State Circuits, 2015

2014
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm<sup>2</sup> all-digital delay-locked loop in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V<sub>TH</sub> Read-Port, and Offset Cell VDD Biasing Techniques.
IEEE J. Solid State Circuits, 2013

2012
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.
Proceedings of the Symposium on VLSI Circuits, 2012

An ultra-low power interface CMOS IC design for biosensor applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
Circuits and System Design of RF Polar Transmitters Using Envelope-Tracking and SiGe Power Amplifiers for Mobile WiMAX.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration.
IEEE J. Solid State Circuits, 2011

A Novel Multifunction CFOA-Based Inverse Filter.
Circuits Syst., 2011

2010
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband.
IEEE J. Solid State Circuits, 2010

Efficiency enhancement and linearity trade-offs for cascode vs. common-emitter SiGe power amplifiers in WiMAX polar transmitters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2009

A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

SiGe Class-E Power Amplifier with Envelope Tracking for Mobile WiMAX/Wibro Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2006
A 14-band Frequency Synthesizer for MB-OFDM UWB Application.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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