Zhiwei Xu

According to our database1, Zhiwei Xu authored at least 49 papers between 2003 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2020
Vector approximate message passing algorithm for compressed sensing with structured matrix perturbation.
Signal Process., 2020

A two-stage approach to estimate CFO and channel with one-bit ADCs.
Signal Process., 2020

Majorization-Minimization-Based Target Localization Problem From Range Measurements.
IEEE Communications Letters, 2020

Point Cloud Features-Based Kernel SVM for Human-Vehicle Classification in Millimeter Wave Radar.
IEEE Access, 2020

2019
Phase Retrieval From Quantized Measurements via Approximate Message Passing.
IEEE Signal Process. Lett., 2019

Grid-less variational Bayesian line spectral estimation with multiple measurement vectors.
Signal Process., 2019

Multi-snapshot Newtonized orthogonal matching pursuit for line spectrum estimation with multiple measurement vectors.
Signal Process., 2019

Asymptotically optimal one-bit quantizer design for weak-signal detection in generalized Gaussian noise and lossy binary communication channel.
Signal Process., 2019

Adaptive Tracking for Beam Alignment between Ship-Borne Digital Phased-Array Antenna and LEO Satellite.
J. Comm. Inform. Networks, 2019

Calibration of a Digital Phased Array by Using NCO Phase Increasing Algorithm.
IEICE Trans. Commun., 2019

Multidimensional Variational Line Spectra Estimation.
CoRR, 2019

Matrix Completion from Quantized Samples via Generalized Sparse Bayesian Learning.
CoRR, 2019

One-bit LFMCW Radar: Spectrum Analysis and Target Detection.
CoRR, 2019

A 21dBm-OP1dB 20.3%-Efficiency -131.8dBm/Hz-Noise X-Band Cartesian-Error-Feedback Transmitter with Fully Integrated Power Amplifier in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Cartesian Error Feedback Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

On the Analysis of the Fisher Information of a Perturbed Linear Model After Random Compression.
IEEE Signal Process. Lett., 2018

Reference Phase Stabilizer for Distributed Underwater Sonar Systems.
Sensors, 2018

A Fast Calibration Method for Phased Arrays by Using the Graph Coloring Theory.
Sensors, 2018

Pencil-on-Paper Sensor for Water Detection.
J. Sensors, 2018

Adaptive one-bit quantisation via approximate message passing with nearest neighbour sparsity pattern learning.
IET Signal Process., 2018

Combined optimisation of waveform and quantisation thresholds for multistatic radar systems.
IET Signal Process., 2018

A 2 GS/s 14-bit current-steering DAC in 65 nm CMOS technology for wireless transmitter.
IEICE Electronic Express, 2018

Binary Sparse Bayesian Learning Algorithm for One-bit Compressed Sensing.
CoRR, 2018

Variational Bayesian Inference of Line Spectral Estimation with Multiple Measurement Vectors.
CoRR, 2018

Newtonized Orthogonal Matching Pursuit for Line Spectrum Estimation with Multiple Measurement Vectors.
CoRR, 2018

2017
Parameter Estimation via Unlabeled Sensing Using Distributed Sensors.
IEEE Communications Letters, 2017

Maximum Likelihood Signal Amplitude Estimation Based on Permuted Blocks of Differently Binary Quantized Observations of a Signal in Noise.
CoRR, 2017

Integrated Circuits for Communications.
IEEE Communications Magazine, 2017

A multi-channel based passive detection strategy for high-speed moving target in the airspace under varying interference.
Proceedings of the 23rd Asia-Pacific Conference on Communications, 2017

2015
Integrated circuits for communications [Series Editorial].
IEEE Communications Magazine, 2015

2013
Topics in integrated circuits for communications [Series Editorial].
IEEE Communications Magazine, 2013

2012
A CMOS Integrated W-band Passive Imager.
IEEE Trans. on Circuits and Systems, 2012

A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications.
J. Solid-State Circuits, 2012

Topics in integrated circuits for communications [Series Editorial].
IEEE Communications Magazine, 2012

Topics in integrated circuits for communications.
IEEE Communications Magazine, 2012

A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range.
IEEE Trans. on Circuits and Systems, 2011

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver.
J. Solid-State Circuits, 2011

A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A Fractional- PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator.
J. Solid-State Circuits, 2010

Topics in integrated circuits for communications.
IEEE Communications Magazine, 2010

A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data link.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
Compact Dual-Band Direct Conversion CMOS Transceiver.
Encyclopedia of Wireless and Mobile Communications, 2008

Delta-Sigma D/A Converter Using Binary- Weighted Digital-to-Analog Differentiator for Second-Order Mismatch Shaping.
IEEE Trans. on Circuits and Systems, 2008

A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases.
J. Solid-State Circuits, 2008

2007
Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2004
A self-synchronized RF-interconnect for 3-dimensional integrated circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


  Loading...