Ziran Zhu

According to our database, Ziran Zhu authored at least 41 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction.

Hao Gu, Youwen Wang, Xinglin Zheng, Keyu Peng, Ziran Zhu, Jianli Chen, Jun Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2025

Fast Training-free Perceptual Image Compression.

Ziran Zhu, Tongda Xu, Minye Huang, Dailan He, Xingtong Ge, Xinjie Zhang, Ling Li, Yan Wang

CoRR, June, 2025

Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB.

Disi Lin, Chuandong Chen, Rongshan Wei, Qinghai Liu, Huan He, Ziran Zhu, Zhifeng Lin, Jianli Chen

Integr., 2025

Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement.

Hao Gu, Xinglin Zheng, Youwen Wang, Keyu Peng, Ziran Zhu, Jun Yang

Proceedings of the Design, Automation & Test in Europe Conference, 2025

Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells.

Zhengzhe Zheng, Yinuo Wu, Keyu Peng, Chao Wang, Ziran Zhu

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Late Breaking Results: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective Floorplanning.

Xinglin Zheng, Hao Gu, Keyu Peng, Youwen Wang, Wenxing Zhu, Ziran Zhu

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Subgraph matching-based reference placement for printed circuit board designs.

Ziran Zhu, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang

J. Supercomput., November, 2024

LAMPlace: Legalization-Aided Reinforcement Learning-Based Macro Placement for Mixed-Size Designs With Preplaced Blocks.

Hao Gu, Jian Gu, Keyu Peng, Ziran Zhu, Ning Xu, Xin Geng, Jun Yang

IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning.

Ziran Zhu, Yuejian Shi, Yangjie Mei, Fuheng Shen, Hong Liu, Jun Yang

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints.

Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting.

Ziran Zhu, Fuheng Shen, Yangjie Mei, Jianli Chen, Jun Yang

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs.

Zijun Li, Ziran Zhu, Huan He, Jianli Chen

Integr., January, 2024

A fast and high-performance global router with enhanced congestion control.

Xiqiong Bai, Yilu Chen, Zhifeng Lin, Min Wei, Zhijie Cai, Ziran Zhu, Jianli Chen

Integr., 2024

Consistency Models Improve Diffusion Inverse Solvers.

Tongda Xu, Ziran Zhu, Dailan He, Yuanyuan Wang, Ming Sun, Ning Li, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang

CoRR, 2024

Noise Dimension of GAN: An Image Compression Perspective.

Ziran Zhu, Tongda Xu, Ling Li, Yan Wang

Proceedings of the IEEE International Conference on Multimedia and Expo, 2024

Idempotence and Perceptual Image Compression.

Tongda Xu, Ziran Zhu, Dailan He, Yanghao Li, Lina Guo, Yuanyuan Wang, Zhe Wang, Hongwei Qin, Yan Wang, Jingjing Liu, Ya-Qin Zhang

Proceedings of the Twelfth International Conference on Learning Representations, 2024

Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints.

Hao Gu, Jian Gu, Keyu Peng, Jun Yang, Ziran Zhu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Variational Label-Correlation Enhancement for Congestion Prediction.

Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Hybrid Reinforcement Learning and Genetic Algorithm for VLSI Floorplanning.

Ke Liu, Jian Gu, Hao Gu, Ziran Zhu

Proceedings of the 15th International Conference on Machine Learning and Computing, 2023

Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints.

Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Efficient Global Optimization for Large Scaled Ordered Escape Routing.

Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints.

Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects.

Jianli Chen, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Timing-Aware Fill Insertions With Design-Rule and Density Constraints.

Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints.

Ziran Zhu, Fuheng Shen, Yangjie Mei, Zhipeng Huang, Jianli Chen, Jun Yang

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

High-performance placement for large-scale heterogeneous FPGAs with clock constraints.

Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Subgraph matching based reference placement for PCB designs: late breaking results.

Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.

Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization.

Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang

ACM Trans. Design Autom. Electr. Syst., 2021

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles.

Ziran Zhu, Zhipeng Huang, Jianli Chen, Longkun Guo

Complex., 2021

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.

Xiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints.

Zhipeng Huang, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, Jianli Chen

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Mixed-Cell-Height Legalization Considering Technology and Region Constraints.

Ziran Zhu, Jianli Chen, Wenxing Zhu, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect.

Ziran Zhu, Zhipeng Huang, Peng Yang, Wenxing Zhu, Jianli Chen, Hanbin Zhou, Senhua Dong

Integr., 2020

An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning.

Zhipeng Huang, Zhifeng Lin, Ziran Zhu, Jianli Chen

IEEE Access, 2020

Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation.

Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

Mixed-cell-height legalization considering technology and region constraints.

Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang

Proceedings of the International Conference on Computer-Aided Design, 2018

Generalized augmented lagrangian and its applications to VLSI global placement.

Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition.

Xingquan Li, Ziran Zhu, Wenxing Zhu

IEEE Trans. Computers, 2017

An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning.

Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu

Integr., 2017

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs.

Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang

Proceedings of the 54th Annual Design Automation Conference, 2017