Jun Yu

Orcid: 0000-0003-4286-9292

Affiliations:

Fudan University, State Key Lab of ASIC & System, Shanghai, China

According to our database¹, Jun Yu authored at least 38 papers between 2019 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Bibliography

2023

Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Access Your Tesla without Your Awareness: Compromising Keyless Entry System of Model 3.

[BibT_eX]

[DOI]

Proceedings of the 30th Annual Network and Distributed System Security Symposium, 2023

eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Edge FPGA-based Onsite Neural Network Training.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

PP-Transformer: Enable Efficient Deployment of Transformers Through Pattern Pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2023

FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Timing-Aware Fill Insertions With Design-Rule and Density Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Implementation of Radiation Hardened Flip-Flops Based on Novel Fishbone Layouts.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

CNN-inspired analytical global placement for large-scale heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Analytical Global Placement for Heterogenous FPGAs Based on the eDensity Model.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Simulation of SEU Response of Advanced 20 nm FDSOI SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs<sup>*</sup>.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells <sup>*</sup>.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Timing-Aware Fill Insertions with Design-Rule and Density Constraints.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

A Horizontal Attack on SM9 Signature Generation.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Computational Intelligence and Security, 2019

Jun Yu

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