Yu-Shen Yang

According to our database¹, Yu-Shen Yang authored at least 16 papers between 2003 and 2014.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2014

Simulation and satisfiability guided counter-example triage for RTL design debugging.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

A failure triage engine based on error trace signature extraction.

[BibT_eX]

[DOI]

Zissis Poulos

Yu-Shen Yang

Andreas G. Veneris

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment.

[BibT_eX]

[DOI]

Yu-Shen Yang

Andreas G. Veneris

Nicola Nicolici

IEEE Trans. Very Large Scale Integr. Syst., 2012

Leveraging reconfigurability to raise productivity in FPGA functional debug.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Automated data analysis techniques for a modern silicon debug environment.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Automating Logic Transformations With Approximate SPFDs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Automated silicon debug data analysis techniques for a hardware data acquisition environment.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

Sequential logic rectifications with approximate SPFDs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Automated data analysis solutions to silicon debug.

[BibT_eX]

[DOI]

Yu-Shen Yang

Nicola Nicolici

Andreas G. Veneris

Proceedings of the Design, Automation and Test in Europe, 2009

2008

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007

Automating Logic Rectification by Approximate SPFDs.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Extraction error modeling and automated model debugging in high-performance custom designs.

[BibT_eX]

[DOI]

Yu-Shen Yang

Andreas G. Veneris

Paul J. Thadikaran

Srikanth Venkataraman

IEEE Trans. Very Large Scale Integr. Syst., 2006

Seamless Integration of SER in Rewiring-Based Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.

[BibT_eX]

[DOI]

Yu-Shen Yang

Andreas G. Veneris

Paul J. Thadikaran

Srikanth Venkataraman

Proceedings of the 2005 Design, 2005

2003

Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Extraction Error Diagnosis and Correction in High-Performance Designs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Yu-Shen Yang

Timeline

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