Aarthy Mani

Orcid: 0000-0002-6159-6974

According to our database1, Aarthy Mani authored at least 15 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
0.85 mW, 8-bit, 1GS/s, 58dB SFDR Cryogenic DAC for Superconducting Qubit Control Applications.
Proceedings of the 20th International SoC Design Conference, 2023

Cryogenic Characterization of 40nm CMOS for Quantum Control Applications.
Proceedings of the 20th International SoC Design Conference, 2023

LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

1V, 1.13μm pixel pitch Liquid Crystal Driver with Charge-Balancing Scheme for SLM Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Stability Analysis of 6T SRAM at Deep Cryogenic Temperature for Quantum Computing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator System.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019


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