Bo Wang

Orcid: 0000-0001-9199-0799

Affiliations:
  • Singapore University of Technology and Design, Department of Information Systems Technology and Design, Singapore
  • National University of Singapore, Singapore (2016 - 2020)
  • Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore (PhD 2015)


According to our database1, Bo Wang authored at least 23 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

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Bibliography

2023
A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron Pruning.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Object-of-Interest Perception in a Reconfigurable Rolling-Crawling Robot.
Sensors, 2022

Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing.
Proceedings of the 19th International SoC Design Conference, 2022

REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
pH Watch - Leveraging Pulse Oximeters in Existing Wearables for Reusable, Real-time Monitoring of pH in Sweat.
Proceedings of the 17th Annual International Conference on Mobile Systems, 2019

HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2017
A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance.
Microelectron. J., 2017

2016
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization.
IEEE J. Solid State Circuits, 2016

2015
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

SRAM devices and circuits optimization toward energy efficiency in multi-V<sub>th</sub> CMOS.
Microelectron. J., 2015

2014
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring.
IEEE J. Solid State Circuits, 2014

0.2 V 8T SRAM with improved bitline sensing using column-based data randomization.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture.
Proceedings of the International SoC Design Conference, 2012

A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012


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