Abdallah Cheikh
Orcid: 0000-0003-4495-5960
According to our database1,
Abdallah Cheikh
authored at least 16 papers
between 2017 and 2023.
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Bibliography
2023
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.
IEEE Access, 2022
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
2021
IEEE Micro, 2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors.
PhD thesis, 2020
CoRR, 2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
2017
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores.
Proceedings of the New Generation of CAS, 2017
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017