Marcello Barbirotta

Orcid: 0000-0002-1902-7188

According to our database1, Marcello Barbirotta authored at least 12 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.
IEEE Access, 2022

Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool.
Proceedings of the Sensors and Microsystems, 2022

2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
ADMM Consensus for Deep LSTM Networks.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020


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