Abhishek Kumar Jain

According to our database1, Abhishek Kumar Jain authored at least 12 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Performance Assessment of Emerging Memories Through FPGA Emulation.
IEEE Micro, 2019

2018
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

A time-multiplexed FPGA overlay with linear interconnect.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays.
CoRR, 2017

2016
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units.
CoRR, 2016

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Throughput oriented FPGA overlays using DSP blocks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

2015
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq.
SIGARCH Computer Architecture News, 2015

Efficient Overlay Architecture Based on DSP Blocks.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform.
Signal Processing Systems, 2014

2013
Microkernel hypervisor for a hybrid ARM-FPGA platform.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013


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