Abhishek Kumar Jain

According to our database, Abhishek Kumar Jain authored at least 20 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Entropy Maximization in Sparse Matrix by Vector Multiplication (max_ESpMV).

Paolo D'Alberto, Abhishek Kumar Jain, Ismail Bustany, Henri Fraisse, Mansimran Benipal

CoRR, 2023

Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs.

Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022

Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation.

Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy

IEEE Trans. Parallel Distributed Syst., 2022

2021

Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform.

Abhishek Kumar Jain, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde

Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020

Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited).

Abhishek Kumar Jain

Proceedings of the SLIP '20: System-Level Interconnect, 2020

High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay.

Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs.

Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Performance Assessment of Emerging Memories Through FPGA Emulation.

Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale

IEEE Micro, 2019

2018

Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments.

Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

A time-multiplexed FPGA overlay with linear interconnect.

Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Architecture centric coarse-grained FPGA overlays

Abhishek Kumar Jain

PhD thesis, 2017

Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays.

Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy

CoRR, 2017

2016

An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units.

Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy

CoRR, 2016

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.

Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Throughput oriented FPGA overlays using DSP blocks.

Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy

Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

2015

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq.

Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell

SIGARCH Comput. Archit. News, 2015

Efficient Overlay Architecture Based on DSP Blocks.

Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform.

Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell

J. Signal Process. Syst., 2014

2013

Microkernel hypervisor for a hybrid ARM-FPGA platform.

Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell

Proceedings of the 24th International Conference on Application-Specific Systems, 2013