Douglas L. Maskell

According to our database1, Douglas L. Maskell authored at least 108 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Time-Multiplexed FPGA Overlay Architectures: A Survey.
ACM Trans. Design Autom. Electr. Syst., 2019

Indicating Asynchronous Multipliers.
CoRR, 2019

Indicating Asynchronous Array Multipliers.
CoRR, 2019

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder.
CoRR, 2019

Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications.
Computers, 2019

2018
A Self-Healing Redundancy Scheme for Mission/Safety-Critical Applications.
IEEE Access, 2018

Hardware Efficient Approximate Adder Design.
Proceedings of the TENCON 2018, 2018

A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme.
Proceedings of the TENCON 2018, 2018

Majority and Minority Voted Redundancy for Safety-Critical Applications.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Indicating Asynchronous Multipliers.
Proceedings of the 2nd European Conference on Electrical Engineering and Computer Science, 2018

A time-multiplexed FPGA overlay with linear interconnect.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency.
IEEE Trans. on Circuits and Systems, 2017

Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis.
CoRR, 2017

Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic.
CoRR, 2017

Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays.
CoRR, 2017

A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units.
CoRR, 2016

DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Throughput oriented FPGA overlays using DSP blocks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?
Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

A racetrack memory based in-memory booth multiplier for cryptography application.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
An Improved Robust Field-Weakeaning Algorithm for Direct-Torque-Controlled Synchronous-Reluctance-Motor Drives.
IEEE Trans. Industrial Electronics, 2015

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq.
SIGARCH Computer Architecture News, 2015

A distributed minority and majority voting based redundancy scheme.
Microelectron. Reliab., 2015

FIE-FCMAC: A novel fuzzy cerebellum model articulation controller (FCMAC) using fuzzy interpolation and extrapolation technique.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Automatic fault detection and diagnosis for photovoltaic systems using combined artificial neural network and analytical based methods.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Efficient Overlay Architecture Based on DSP Blocks.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform.
Signal Processing Systems, 2014

The iDEA DSP Block-Based Soft Processor for FPGAs.
TRETS, 2014

HFL micro inverter with front-end diode clamped multi-level inverter and half-wave cycloconverter.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

Soft-switching single inductor current-fed push-pull converter for PV applications.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

A uniform implementation scheme for evolutionary optimization algorithms and the experimental implementation of an ACO based MPPT for PV systems under partial shading.
Proceedings of the 2014 IEEE Symposium on Computational Intelligence Applications in Smart Grid, 2014

2013
Reconfigurable Accelerator for the Word-Matching Stage of BLASTN.
IEEE Trans. VLSI Syst., 2013

C2FPGA - A dependency-timing graph design methodology.
J. Parallel Distributed Comput., 2013

A hybrid short read mapping accelerator.
BMC Bioinformatics, 2013

Fuzzy interpolation and extrapolation using shift ratio and overall weight measurement based on areas of fuzzy sets.
Proceedings of the 13th UK Workshop on Computational Intelligence, 2013

High-frequency-link micro-inverter with front-end current-fed half-bridge boost converter and half-wave cycloconverter.
Proceedings of the IECON 2013, 2013

A simple and efficient hybrid maximum power point tracking method for PV systems under partially shaded condition.
Proceedings of the IECON 2013, 2013

Current-controlled resonant circuit based photovoltaic micro-inverter with half- wave cycloconverter.
Proceedings of the 2013 IEEE Industry Applications Society Annual Meeting, 2013

Microkernel hypervisor for a hybrid ARM-FPGA platform.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Fourth Workshop on using Emerging Parallel Architectures.
Proceedings of the International Conference on Computational Science, 2012

CUSHAW: a CUDA compatible short read aligner to large genomes based on the Burrows-Wheeler transform.
Bioinformatics, 2012

Chebyshev Functional Link Neural Network-based modeling and experimental verification for photovoltaic arrays.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

A flann-based controller for maximum power point tracking in PV systems under rapidly changing conditions.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

iDEA: A DSP block based FPGA soft processor.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

An FPGA aligner for short read mapping.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Accelerating short read mapping on an FPGA (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A lean FPGA soft processor built using a DSP block.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Third Workshop on using Emerging Parallel Architectures.
Proceedings of the International Conference on Computational Science, 2011

A Novel Fuzzy Associative Memory Architecture for Stock Market Prediction and Trading.
IJFSA, 2011

Parallelized short read assembly of large genomes using de Bruijn graphs.
BMC Bioinformatics, 2011

DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI.
BMC Bioinformatics, 2011

CompleteMOTIFs: DNA motif discovery platform for transcription factor binding experiments.
Bioinformatics, 2011

Estimation of external quantum efficiency for multi-junction solar cells under influence of charged particles using artificial neural networks.
Proceedings of the IEEE International Conference on Systems, 2011

Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile Applications.
Proceedings of the International Symposium on Electronic System Design, 2011

An Ultrafast Scalable Many-Core Motif Discovery Algorithm for Multiple GPUs.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
EpiList II: Closing the Loop in the Development of Generic Cognitive Skills.
IEEE Trans. Systems, Man, and Cybernetics, Part A, 2010

Second Workshop on using Emerging Parallel Architectures.
Proceedings of the International Conference on Computational Science, 2010

CUDA-MEME: Accelerating motif discovery in biological sequences using CUDA-enabled graphics processing units.
Pattern Recognit. Lett., 2010

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth.
Integr., 2010

MSAProbs: multiple sequence alignment based on pair hidden Markov models and partition function posterior probabilities.
Bioinformatics, 2010

A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

High level event driven thermal estimation for thermal aware task allocation and scheduling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
High Speed Biological Sequence Analysis With Hidden Markov Models on Reconfigurable Platforms.
IEEE Trans. Information Technology in Biomedicine, 2009

Parallel reconstruction of neighbor-joining trees for large multiple sequence alignments using CUDA.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Workshop on Using Emerging Parallel Architectures for Computational Science.
Proceedings of the Computational Science, 2009

Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

A Reconfigurable Bloom Filter Architecture for BLASTN.
Proceedings of the Architecture of Computing Systems, 2009

2008
A unified architecture for a public key cryptographic coprocessor.
J. Syst. Archit., 2008

Multiplierless multi-standard SDR channel filters.
Proceedings of the International Workshop on Multimedia Signal Processing, 2008

Efficient multiplierless channel filters for multi-standard SDR.
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2007
Fast Identification of Custom Instructions for Extensible Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Supporting multiple-input, multiple-output custom functions in configurable processors.
Journal of Systems Architecture, 2007

Design of efficient multiplierless FIR filters.
IET Circuits, Devices & Systems, 2007

Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System.
EURASIP J. Emb. Sys., 2007

C-Based Design Methodology for FPGA Implementation of ClustalW MSA.
Proceedings of the Pattern Recognition in Bioinformatics, 2007

An Embedded Systems graduate education for Singapore.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007

Type-2 GA-TSK fuzzy neural network.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007

2006
Adaptive subsample delay estimation using windowed correlation.
IEEE Trans. on Circuits and Systems, 2006

A technique for expressing IT security objectives.
Inf. Softw. Technol., 2006

High-speed Multiple Sequence Alignment on a reconfigurable platform.
IJBRA, 2006

The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware.
Proceedings of the Computational Science, 2006

Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Execution Objects for Dynamically Reconfigurable FPGA Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

A Brain Inspired Fuzzy Neuro-predictor for Bank Failure Analysis.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

FCMAC-AARS: A Novel FNN Architecture for Stock Market Prediction and Trading.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors.
Proceedings of the Architecture of Computing Systems, 2006

Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Reconfigurable architectures for bio-sequence database scanning on FPGAs.
IEEE Trans. on Circuits and Systems, 2005

Adaptive subsample delay estimation using a modified quadrature phase detector.
IEEE Trans. on Circuits and Systems, 2005

Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW.
Bioinformatics, 2005

A reconfigurable architecture for scanning biosequence databases.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Multiple Sequence Alignment on an FPGA.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

An FPGA Model for Developing Dynamic Circuit Computing.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Hyper customized processors for bio-sequence database scanning on FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Biological Sequence Analysis with Hidden Markov Models on an FPGA.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
A hardware efficient implementation of an adaptive subsample delay estimator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
The discrete-time quadrature subsample estimation of delay.
IEEE Trans. Instrumentation and Measurement, 2002

2000
A frequency modulated envelope delay FSCW radar for multiple-target applications.
IEEE Trans. Instrumentation and Measurement, 2000

1999
The estimation of subsample time delay of arrival in the discrete-time measurement of phase delay.
IEEE Trans. Instrumentation and Measurement, 1999


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