Chirag Ravishankar

According to our database, Chirag Ravishankar authored at least 14 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.

Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.

Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs.

Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2019

Xilinx Adaptive Compute Acceleration Platform: Versal^TM Architecture.

Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs.

Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde

Proceedings of the International Conference on Field-Programmable Technology, 2018

Placement Strategies for 2.5D FPGA Fabric Architectures.

Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2012

Raising FPGA Logic Density Through Synthesis-Inspired Architecture.

Jason Helge Anderson, Qiang Wang, Chirag Ravishankar

IEEE Trans. Very Large Scale Integr. Syst., 2012

FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture.

Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

FPGA power reduction by guarded evaluation considering physical information.

Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms.

Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip.

Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only).

Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Parallel FPGA technology mapping using multi-core architectures.

Andrew A. Kennings, Chirag Ravishankar

Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010

FPGA power reduction by guarded evaluation.

Jason Helge Anderson, Chirag Ravishankar

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010