Adrián Barredo

Orcid: 0000-0001-9435-3234

According to our database1, Adrián Barredo authored at least 9 papers between 2019 and 2022.

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Bibliography

2022
Compiler-Assisted Compaction/Restoration of SIMD Instructions.
IEEE Trans. Parallel Distributed Syst., 2022

2021
Novel techniques to improve the performance and the energy of vector architectures.
PhD thesis, 2021

PLANAR: a programmable accelerator for near-memory data rearrangement.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies.
J. Supercomput., 2020

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86.
Future Gener. Comput. Syst., 2020

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
POSTER: An Optimized Predication Execution for SIMD Extensions.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019


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