Julian Pavon

Orcid: 0000-0002-8291-509X

Affiliations:
  • Barcelona Supercomputing Center, Spain


According to our database1, Julian Pavon authored at least 12 papers between 2019 and 2026.

Collaborative distances:

Timeline

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Bibliography

2026
Different Perspectives of Memory System Simulation.
CoRR, April, 2026

UPSORT: Design and Analysis of Processing-in-Memory Sorting Algorithms using UPMEM.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026

2025
Halis: A Hardware-Software Co-Designed Near-Cache Accelerator for Graph Pattern Mining.
IEEE Comput. Archit. Lett., 2025

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2024
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.
ACM Trans. Archit. Code Optim., June, 2023

VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023


2022

2021
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

2019
A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019


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