Alexandra Jimborean

Orcid: 0000-0001-8642-2447

According to our database1, Alexandra Jimborean authored at least 42 papers between 2011 and 2024.

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Bibliography

2024
Wrong-Path-Aware Entangling Instruction Prefetcher.
IEEE Trans. Computers, February, 2024

Alternate Path μ-op Cache Prefetching.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

Preface ASAP 2023.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
Compiler-Assisted Compaction/Restoration of SIMD Instructions.
IEEE Trans. Parallel Distributed Syst., 2022

Analysing software prefetching opportunities in hardware transactional memory.
J. Supercomput., 2022

CONVOLVE: Smart and seamless design of smart edge processors.
CoRR, 2022

Exploring Instruction Fusion Opportunities in General Purpose Processors.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Composite Instruction Prefetching.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
A Cost-Effective Entangling Prefetcher for Instructions.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution.
IEEE Trans. Computers, 2020

Evaluating the Potential Applications of Quaternary Logic for Approximate Computing.
ACM J. Emerg. Technol. Comput. Syst., 2020

The Entangling Instruction Prefetcher.
IEEE Comput. Archit. Lett., 2020

Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

Regional Out-of-Order Writes in Total Store Order.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Efficient invisible speculative execution through selective delay and value prediction.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Efficient thread/page/parallelism autotuning for NUMA systems.
Proceedings of the ACM International Conference on Supercomputing, 2019

Ghost loads: what is the cost of invisible speculation?
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation.
IEEE Trans. Parallel Distributed Syst., 2018

Static Instruction Scheduling for High Performance on Limited Hardware.
IEEE Trans. Computers, 2018

Computer scientists in action: Alexandra Jimborean, computer architecture.
XRDS, 2018

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

2017
Decoupled Access-Execute on ARM big.LITTLE.
CoRR, 2017

A dedicated private-shared cache design for scalable multiprocessors.
Concurr. Comput. Pract. Exp., 2017

Transcending Hardware Limits with Software Out-of-Order Processing.
IEEE Comput. Archit. Lett., 2017

Clairvoyance: look-ahead compile-time scheduling.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

Automatic detection of extended data-race-free regions.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

2016
A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence.
IEEE Trans. Parallel Distributed Syst., 2016

Profiling-Assisted Decoupled Access-Execute.
CoRR, 2016

Multiversioned decoupled access-execute: the key to energy-efficient compilation of general-purpose programs.
Proceedings of the 25th International Conference on Compiler Construction, 2016

2015
A Dual-Consistency Cache Coherence Protocol.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

2014
Dynamic and Speculative Polyhedral Parallelization Using Compiler-Generated Skeletons.
Int. J. Parallel Program., 2014

Software-controlled processor stalls for time and energy efficient data locality optimization.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Speculative Program Parallelization with Scalable and Decentralized Runtime Verification.
Proceedings of the Runtime Verification - 5th International Conference, 2014

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Dynamic and Speculative Polyhedral Parallelization of Loop Nests Using Binary Code Patterns.
Proceedings of the International Conference on Computational Science, 2013

Online Dynamic Dependence Analysis for Speculative Polyhedral Parallelization.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

2012
Adapting the polytope model for dynamic and speculative parallelization. (Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice).
PhD thesis, 2012

Adapting the polyhedral model as a framework for efficient speculative parallelization.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

VMAD: An Advanced Dynamic Program Analysis and Instrumentation Framework.
Proceedings of the Compiler Construction - 21st International Conference, 2012

2011
VMAD: A virtual machine for advanced dynamic analysis of programs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011


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