Ajit Dingankar

According to our database, Ajit Dingankar authored at least 15 papers between 1988 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories.

Guantao Liu, Tim Schmidt, Rainer Dömer, Ajit Dingankar, Desmond Kirkpatrick

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2010

Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback.

Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar

EURASIP J. Embed. Syst., 2010

2009

Power estimation methodology for a high-level synthesis framework.

Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.

Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

MMV: A Metamodeling Based Microprocessor Validation Environment.

Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures.

Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Model Based Test Generation for Microprocessor Architecture Validation.

Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Assertion-Based Modal Power Estimation.

Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar

Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Model-driven test generation for system level validation.

Deepak Mathaikutty, Sumit Ahuja, Ajit Dingankar, Sandeep K. Shukla

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Metamodeling based Framework for Architectural Modeling and Simulator Generation.

Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla

Proceedings of the Forum on specification and Design Languages, 2007

Design fault directed test generation for microprocessor validation.

Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

MMV: Metamodeling Based Microprocessor Valiation Environment.

Ajit Dingankar, Deepak Mathaikutty, Sreekumar V. Kodakara, Sandeep K. Shukla, David J. Lilja

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

1995

On Error Bounds for Neural Network Approximation.

Ajit Dingankar, Irwin W. Sandberg

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1988

Automated Design and Analysis System for Design of Custom Orthopedic Implants.

R. Larry Dooley, G. Heimke, Ajit Dingankar, E. Berg, E. Kimbrough

Proceedings of the First International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1988, June 1-3, 1988, Tullahoma, TN, USA. ACM, 1988, 1988

Orthopedic implant design, analysis, and manufacturing system.

R. Larry Dooley, Ajit Dingankar, G. Heimke, E. Berg

Proceedings of the First Annual IEEE Symposium on Computer-Based Medical Systems (CBMS'88), 1988