Ajit Dingankar

According to our database1, Ajit Dingankar authored at least 15 papers between 1988 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback.
EURASIP J. Emb. Sys., 2010

Power estimation methodology for a high-level synthesis framework.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

MMV: A Metamodeling Based Microprocessor Validation Environment.
IEEE Trans. VLSI Syst., 2008

A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Model Based Test Generation for Microprocessor Architecture Validation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Assertion-Based Modal Power Estimation.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Model-driven test generation for system level validation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Metamodeling based Framework for Architectural Modeling and Simulator Generation.
Proceedings of the Forum on specification and Design Languages, 2007

Design fault directed test generation for microprocessor validation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

MMV: Metamodeling Based Microprocessor Valiation Environment.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

On Error Bounds for Neural Network Approximation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Automated Design and Analysis System for Design of Custom Orthopedic Implants.
Proceedings of the First International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1988, June 1-3, 1988, Tullahoma, TN, USA. ACM, 1988, 1988

Orthopedic implant design, analysis, and manufacturing system.
Proceedings of the First Annual IEEE Symposium on Computer-Based Medical Systems (CBMS'88), 1988