John Dielissen

According to our database1, John Dielissen authored at least 13 papers between 2001 and 2008.

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Bibliography

2008
Multistandard FEC Decoders for Wireless Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007
Non-fractional parallelism in LDPC decoder implementations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Low cost LDPC decoder for DVB-S2.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Æthereal Network on Chip: Concepts, Architectures, and Implementations.
IEEE Des. Test Comput., 2005

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.
Proceedings of the 2005 Design, 2005

2004
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
Proceedings of the 2004 Design, 2004

A Scalable Architecture for LDPC Decodin.
Proceedings of the 2004 Design, 2004

2003
Bringing communication networks on a chip: test and verification implications.
IEEE Commun. Mag., 2003

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
Proceedings of the 2003 Design, 2003

Guaranteeing the Quality of Services in Networks on Chip.
Proceedings of the Networks on Chip, 2003

2002
Breaking an application specific instruction-set processor: the first step towards embedded software testing.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Power-efficient layered turbo decoder processor.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001


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