Alessandro Palumbo

According to our database, Alessandro Palumbo authored at least 13 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules.

Alessandro Palumbo, Rubén Salvador

CoRR, June, 2025

Human-in-the-Loop: Legal Knowledge Formalization in Attempto Controlled English.

Grazia Garzo, Alessandro Palumbo

Proceedings of the 13th International Symposium on Digital Forensics and Security, 2025

Legal & Ethical Implications of Predictive Digital Techniques in the Judicial Criminal Proceedings.

Grazia Garzo, Alessandro Palumbo

Proceedings of the 13th International Symposium on Digital Forensics and Security, 2025

Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection.

Alessandro Palumbo, Rubén Salvador

Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions, 2025

2024

Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores.

Stefano Ribes, Fabio Malatesta, Grazia Garzo, Alessandro Palumbo

Proceedings of the 10th International Conference on Information Systems Security and Privacy, 2024

2023

Towards Dependable RISC-V Cores for Edge Computing Devices.

Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses.

Alessandro Palumbo, Marco Ottavi, Luca Cassano

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes.

Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches.

Kerem Arikan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi, Oguz Ergin, Marco Ottavi

IEEE Trans. Very Large Scale Integr. Syst., 2022

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer.

Alessandro Palumbo, Luca Cassano, Bruno Luzzi, José Alberto Hernández, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi

J. Syst. Archit., 2022

hXDP: Efficient software packet processing on FPGA NICs.

Marco Spaziani Brunella, Giacomo Belocchi, Marco Bonola, Salvatore Pontarelli, Giuseppe Siracusano, Giuseppe Bianchi, Aniello Cammarano, Alessandro Palumbo, Luca Petrucci, Roberto Bifulco

Commun. ACM, 2022

Is RISC-V ready for Space? A Security Perspective.

Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses.

Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021