Salvatore Pontarelli
Orcid: 0000-0002-3626-6404
According to our database1,
Salvatore Pontarelli
authored at least 143 papers
between 2001 and 2023.
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Bibliography
2023
Proc. ACM Meas. Anal. Comput. Syst., December, 2023
IEEE/ACM Trans. Netw., June, 2023
IEEE Trans. Emerg. Top. Comput., 2023
SPADA: A Sparse Approximate Data Structure Representation for Data Plane Per-flow Monitoring.
PACMNET, 2023
Proceedings of the Companion of the 19th International Conference on emerging Networking EXperiments and Technologies, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
IEEE Trans. Netw. Serv. Manag., December, 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Commun. Mag., 2022
Proceedings of the 3rd International CoNEXT Student Workshop, 2022
2021
IEEE Netw. Lett., 2021
Comput. Networks, 2021
Proceedings of the 24th Conference on Innovation in Clouds, 2021
Proceedings of the CoNEXT '21: The 17th International Conference on emerging Networking EXperiments and Technologies, Virtual Event, Munich, Germany, December 7, 2021
2020
Cuckoo Filters and Bloom Filters: Comparison and Application to Packet Classification.
IEEE Trans. Netw. Serv. Manag., 2020
IEEE Commun. Lett., 2020
Proceedings of the 2020 IEEE Conference on Network Function Virtualization and Software Defined Networks, 2020
Proceedings of the 23rd Conference on Innovation in Clouds, 2020
Europe's First 5G-Ready Railway Trial Utilizing Integrated Optical Passive WDM Access and Broadband Millimeter-Wave to Deliver Multi-Gbit/s Seamless Connectivity.
Proceedings of the European Conference on Optical Communications, 2020
When filtering is not possible caching negatives with fingerprints comes to the rescue.
Proceedings of the CoNEXT '20: The 16th International Conference on emerging Networking EXperiments and Technologies, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE/ACM Trans. Netw., 2019
IEEE Trans. Netw. Serv. Manag., 2019
Proc. IEEE, 2019
Smashing OpenFlow's "atomic" actions: Programmable data plane packet manipulation in hardware.
Int. J. Netw. Manag., 2019
IEEE Commun. Lett., 2019
High-speed data plane and network functions virtualization by vectorizing packet processing.
Comput. Networks, 2019
Proceedings of the 6th International Conference on Software Defined Systems, 2019
Proceedings of the 16th USENIX Symposium on Networked Systems Design and Implementation, 2019
Proceedings of the European Conference on Networks and Communications, 2019
Proceedings of the European Conference on Networks and Communications, 2019
Proceedings of the European Conference on Networks and Communications, 2019
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology.
IEEE Trans. Emerg. Top. Comput., 2018
IEEE Commun. Mag., 2018
Comput. Commun. Rev., 2018
Proceedings of the ACM SIGCOMM 2018 Conference on Posters and Demos, 2018
Proceedings of the IEEE INFOCOM 2018, 2018
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018
Proceedings of the 2018 European Conference on Networks and Communications, 2018
2017
StreaMon: A Data-Plane Programming Abstraction for Software-Defined Stream Monitoring.
IEEE Trans. Dependable Secur. Comput., 2017
Proceedings of the Digital Communication. Towards a Smart and Secure Future Internet, 2017
Proceedings of the Symposium on SDN Research, 2017
On offloading programmable SDN controller tasks to the embedded microcontroller of stateful SDN dataplanes.
Proceedings of the 2017 IEEE Conference on Network Softwarization, 2017
Smashing SDN "built-in" actions: Programmable data plane packet manipulation in hardware.
Proceedings of the 2017 IEEE Conference on Network Softwarization, 2017
Demo: Implementing advanced network functions with stateful programmable data planes.
Proceedings of the 2017 IEEE International Symposium on Local and Metropolitan Area Networks, 2017
Implementing advanced network functions for datacenters with stateful programmable data planes.
Proceedings of the 2017 IEEE International Symposium on Local and Metropolitan Area Networks, 2017
2016
IEEE Trans. Computers, 2016
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
IEEE Trans. Computers, 2016
Inf. Process. Lett., 2016
IEEE Internet Comput., 2016
Towards a Stateful Forwarding Abstraction to Implement Scalable Network Functions in Software and Hardware.
CoRR, 2016
Open Packet Processor: a programmable architecture for wire speed platform-independent stateful in-network processing.
CoRR, 2016
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016
Proceedings of the European Conference on Networks and Communications, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Computers, 2015
IEEE Des. Test, 2015
Proceedings of the 2015 IEEE Online Conference on Green Communications, 2015
Proceedings of the 16th IEEE International Conference on High Performance Switching and Routing, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. Reliab., 2014
Inf. Process. Lett., 2014
Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing.
IEEE Commun. Lett., 2014
Proceedings of the 2014 26th International Teletraffic Congress (ITC), 2014
Complementary resistive switch based stateful logic operations using material implication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Computers, 2013
Error Detection and Correction in Content Addressable Memories by Using Bloom Filters.
IEEE Trans. Computers, 2013
IEEE Trans. Computers, 2013
F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013
2012
J. Signal Process. Syst., 2012
On the use of Karatsuba formula to detect errors in GF((2(sup)n(/sup))(sup)2(/sup)) multipliers.
IET Circuits Devices Syst., 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
Proceedings of the Traffic Monitoring and Analysis - Third International Workshop, 2011
Anti-evasion Technique for Packet Based Pre-filtering for Network Intrusion Detection Systems (Poster).
Proceedings of the Traffic Monitoring and Analysis - Third International Workshop, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
J. Electron. Test., 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Computers, 2007
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.
IEEE Trans. Computers, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
J. Electron. Test., 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.
Proceedings of the 2005 Design, 2005
2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
2001
Development of a dynamic routing system for a fault tolerant solid state mass memory.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001