Héctor Pettenghi

According to our database1, Héctor Pettenghi authored at least 23 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2018
Efficient RNS Reverse Converters for Moduli Sets with Dynamic Ranges Up to \((10n+1)\) -bit.
CSSP, 2018

2017
Efficient implementation of modular multiplication by constants applied to RNS reverse converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Method for designing two levels RNS reverse converters for large dynamic ranges.
Integration, 2016

RNS reverse converters for moduli sets with dynamic ranges of 9n-bit.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
RNS reverse converters based on the new Chinese Remainder Theorem I.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Efficient Method for Designing Modulo {2n ± k} Multipliers.
Journal of Circuits, Systems, and Computers, 2014

Method for Designing Efficient Mixed Radix Multipliers.
CSSP, 2014

Method for designing multi-channel RNS architectures to prevent power analysis SCA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Method to Design General RNS Reverse Converters for Extended Moduli Sets.
IEEE Trans. on Circuits and Systems, 2013

RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit.
IEEE Trans. on Circuits and Systems, 2013

Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.
IET Circuits, Devices & Systems, 2013

DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
RNS Arithmetic Units for Modulo {2^n+-k}.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010
An improved RNS generator 2n +/- k based on threshold logic.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2009
Operation Limits for RTD-Based MOBILE Circuits.
IEEE Trans. on Circuits and Systems, 2009

2008
Using multi-threshold threshold gates in RTD-based logic design: A case study.
Microelectronics Journal, 2008

A novel contribution to the RTD-based threshold logic family.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Non Return Mobile Logic Family.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors.
IEEE Trans. on Circuits and Systems, 2006

Self-latching operation limits for MOBILE circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Logic Models Supporting the Design of MOBILE-based RTD Circuits.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Programmable logic gate based on resonant tunnelling devices.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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