Anatoly Koyfman

According to our database1, Anatoly Koyfman authored at least 13 papers between 1999 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2016
Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Using Graph-Based CSP to Solve the Address Translation Problem.
Proceedings of the Principles and Practice of Constraint Programming, 2016

2014

2013
Improving Post-silicon Validation Efficiency by Using Pre-generated Data.
Proceedings of the Hardware and Software: Verification and Testing, 2013

2012
Leveraging Accelerated Simulation for Floating-Point Regression.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Checking architectural outputs instruction-by-instruction on acceleration platforms.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Simulation-Based Verification of Floating-Point Division.
IEEE Trans. Computers, 2011

Injecting Floating-Point Testing Knowledge into Test Generators.
Proceedings of the Hardware and Software: Verification and Testing, 2011

2009
Implementation Specific Verification of Divide and Square Root Instructions.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2006
DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2003
DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

FPgen - a test generation framework for datapath floating-point verification.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

1999
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture.
Proceedings of the 36th Conference on Design Automation, 1999


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