Debapriya Chatterjee

According to our database1, Debapriya Chatterjee authored at least 16 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Return-oriented programming protection in the IBM POWER10.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2018
Addressing verification challenges of heterogeneous systems based on IBM POWER9.
IBM J. Res. Dev., 2018

2014
ArChiVED: Architectural checking via event digests for high performance validation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.
PhD thesis, 2013

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On the use of GP-GPUs for accelerating compute-intensive EDA applications.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Approximating checkers for simulation acceleration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SAGA: SystemC acceleration on GPU architectures.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Checking architectural outputs instruction-by-instruction on acceleration platforms.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

SystemC simulation on GP-GPUs: CUDA vs. OpenCL.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Gate-Level Simulation with GPU Computing.
ACM Trans. Design Autom. Electr. Syst., 2011

Simulation-based signal selection for state restoration in silicon debug.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
EQUIPE: Parallel equivalence checking with GP-GPUs.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Activity-based refinement for abstraction-guided simulation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

GCS: High-performance gate-level simulation with GPGPUs.
Proceedings of the Design, Automation and Test in Europe, 2009

Event-driven gate-level simulation with GP-GPUs.
Proceedings of the 46th Design Automation Conference, 2009


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